`timescale 1ns / 1ps
/*--------------------------------------------------------------------*\
FileName        : test_top.v
Author          ：hpy
Email           ：yuan_hp@qq.com
Date            ：2024年07月06日
Description     ：
\*--------------------------------------------------------------------*/
module test_top (
    input clk,
    input rst_n , 
    output reg[7:0] o_pwm
);
 
/* ------------------ function -------------------- */
 
/* -------------------- param --------------------- */
 
/*---------------------- reg ---------------------- */

/*----------------------- wire ---------------------*/
 
/*--------------------- assign ---------------------*/

/*---------------------- blk -----------------------*/
wire interrupt ;
// cbb_timer_ena  u_cbb_timer_ena(clk, rst_n ,32'd4 , interrupt) ; 

wire [7:0] out_port , port_id ; 
reg  [7:0] in_port ;
wire write_strobe  ;

psm_soc #(
    .memfile("test.hex") ,  
    .memnum ( 1024)  , 
	.stack_size  (32) ,  // 1 ~ 32 
	.scratch_size( 256) // 1 ~ 256  
) psm_soc_u1 (
    .clk (clk) ,
    .reset(~rst_n ) ,
    .in_port (in_port ),
    .out_port(out_port) ,
    .port_id (port_id ),
    .write_strobe(write_strobe) ,
    .interrupt(interrupt) ,
    .interrupt_ack()
); 


reg [7:0] pio = 0 ;
reg [1:0] pio_bito_ff ;
always@ (posedge clk) begin
    if(write_strobe)begin //
        case(port_id)
            8'hff:  begin 
                pio  <= out_port;
            end 
            default:  ;
        endcase 
    end 
end  
reg pio_d0 = 1'b0;
always@(posedge clk)begin 
    pio_d0 <= pio[0] ;
    pio_bito_ff <= {pio_bito_ff[0],pio_d0 } ;
end 
assign interrupt = pio_bito_ff==2'b01 ;


//输入口
always @(*)begin
    case(port_id)
        8'hff: in_port = pio;
        default:in_port = 8'h00;
    endcase
end

endmodule
 
